The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. For fabricating complex integrated circuits, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed above a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, includes so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. These regions are embedded or are formed in a well region, which has an appropriate doping level and profile so as to adjust the basic transistor characteristics, such as threshold voltage and the like. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the distance between the source and drain regions, which is also referred to as channel length. Therefore, reducing the feature sizes and in particular the gate length (and, thus, the channel length) of the field effect transistors has been an important design criterion.
In addition to other advantages, silicon-on-insulator (SOI) technology has continuously been gaining in importance for manufacturing MOS transistors due to reduced parasitic capacitance of the PN junctions in SOI transistors, thereby allowing higher switching speeds compared to bulk transistors. In SOI transistors, the semiconductor region or active region, in which the drain and source regions as well as the channel region are located, also referred to as the body, is dielectrically encapsulated. This configuration provides significant advantages, but also gives rise to a plurality of issues. Bulk devices have bodies that are electrically connected to the substrate and are maintained at a specified potential when a specified potential is applied to the substrate. Unlike bulk devices, the body or well of SOI transistors is not connected to a specified reference potential, and, hence, the body's potential may usually float due to the accumulation of minority charge carriers, unless appropriate countermeasures are taken.
These floating body effects result in drain current “kink” effect, abnormal threshold slope, low drain breakdown voltage, drain current transients, and noise overshoot. The “kink” effect originates from impact ionization. When an SOI MOSFET is operated at a large drain-to-source voltage, channel electrons cause impact ionization near the drain end of the channel. Holes build up in the body of the device, raising body potential and thereby raising threshold voltage. This increases the MOSFET current causing a “kink” in the current vs. voltage (I-V) curves. It is thus desirable to eliminate floating body effects.
Accordingly, it is desirable to provide improved SOI integrated circuit structures and methods for fabricating SOI integrated circuits that include body contact features that reduce or eliminate the floating body effects and the negative performance consequences that result from the presence thereof. It further is desirable to provide methods for fabricating the same that are relatively inexpensive to implement and have wide applicability across a variety of integrated circuit designs. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.